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From: =?UTF-8?B?6JSh5YKz6LOH?= <imruinland.cs00@g2.nctu.edu.tw>
Date: Wed, 1 Apr 2020 00:20:44 +0800
Message-ID: <CA+E1uJr9M=Yp-DettRTYjBn_SVyru85AxdBHF-3oiYtEUgycSw@mail.gmail.com>
Subject: Fwd: [alpine-devel] Alpine Linux on RISC-V
To: ~alpine/devel@lists.alpinelinux.org
Content-Type: text/plain; charset="UTF-8"

I forgot to turn on plain-text mode so the mail got rejected.
Forwarding the following message - -

Hi all,
sorry again for bumping such an ancient mail thread.

It's been a while since my last e-mail.
(This is my private email for my pastime and hobby projects.)
During these days, I've upgraded Drew and others' work on musl riscv32
port from 1.1.21 to 1.2.0.
And I've successfully ported and booted Alpine 3.9 on an open-sourced
RV32 platform - - Litex/VexRiscv. [1]
The FPGA board I used is a Lattice ECP5-5G Versa stock evaluation
board, which can be purchased on Mouser/DigiKey. [2]

Here's the recorded footage  - -
https://asciinema.org/a/315205

Currently, the whole alpine-base is bootstrapped.
Like I myself, I believe most of people here will be more keen to a
publicly accessible platform

Somehow, I've already acknowledged that Rich Felker declined to merge
RV32 port of musl long time ago.
The reason is stated as "the main blocker for riscv32 has been that
the kernel has not declared it a stable ABI yet." [3]

I'm not quite sure about what exactly is "declaring a stable ABI."
I will ask about this issue on musl's mailing list maybe a couple of days later.

Yet I'm pretty sure that there's a tons of work needed to be done for
verifying an Alpine port.
I would like to know that if there's a list of requirements for
testing/accepting a new architecture port?

Best regards,
Ruinland ChuanTzu Tsai

[1] https://github.com/litex-hub/linux-on-litex-vexriscv
[3] https://www.latticesemi.com/en/Products/DevelopmentBoardsAndKits/ECP55GVersaDevKit
[2] https://www.openwall.com/lists/musl/2020/03/12/2